1. Field
Various embodiments of the present invention relate to an electronic circuit design technology, and more particularly, to a preamplifier, and a comparator and an analog-to-digital converting apparatus including the same.
A two-step single-slope analog-to-digital converter (ADC) will be described as an example. However, embodiments of the present invention may be applied to a multi-step multi-slope ADC as well as a multi-step single-slope ADC, and may also be applied to a system requiring a high-speed multi-step single-slope ADC and a high-speed multi-step multi-slope ADC. Thus, the present invention is not limited to the two-step single-slope ADC.
2. Description of the Related Art
Methods for two-step (or multi-step) single-slope A/D conversion are disclosed in related art documents such as “Alexey Yakovlev, ‘Double-Ramp ADC for CMOS Sensors’ U.S. Pat. No. 6,670,904 B1, Dec. 30, 2003” and “Seunghyun Lim, ‘A High-Speed CMOS Image Sensor with Column-Parallel Two-Step Single-Slope ADCs’, IEEE Trans. Electron Devices, vol. 56, no. 3, pp. 393-398, March, 2009”.
In the related arts, a coarse ramping voltage for most significant bit (MSB) conversion is stored in the top plate of a capacitor, an input terminal for fine ramping is coupled to the bottom plate of the capacitor during fine ramping for least significant bit (LSB) conversion, and then the voltage stored with a floating state in the top plate of the capacitor changes according to a fine ramping voltage.
The above-described related arts have a fundamental concern in that the slopes of the coarse ramping voltage and the fine ramping voltage which are inputted to a comparator during the coarse ramping and the fine ramping may differ depending on the conversion process.
In general, when a two-step single-slope analog-to-digital converter (ADC) is implemented, the preservability of input signals significantly influences the linearity of the ADC.
In a conventional ADC, however, change of an output node of a comparator may exert influence on signals stored in a floated input terminal of the comparator due to a coupling by overlap parasitic capacitance, thereby causing distortion. Such distortion may cause a linearity error of the ADC.